Leak-Free Machine Learning for Hardware Trojan Detection at RTL

Abstract

Hardware Trojans (HTs) are considered a significant challenge to contemporary IC production lines since any malicious changes made during either the design phase or IC fabrication process are impossible to identify post production. This study proposes an ML model that automatically detects HTs using only the Register Transfer Level (RTL) Verilog code without needing physical verification or having a golden design to compare against. While there are numerous RTL models available, they are limited in their use of features and may be prone to data leakage. The proposed model utilizes a pipeline that avoids data leakage by performing SMOTE operations only within training folds. Thirty five features are extracted from each design, ranging from structural properties to operational behavior and signal connections. Five classifiers Random Forest (RF), Gradient Boosting (GB), XGBoost, Support Vector Machine (SVM), and Logistic Regression (LR) are evaluated using stratified cross-validation on a dataset of 2,150 RTL designs (76.7% Trojan, 23.3% clean). Among them, the RF model achieves the best performance, with a cross-validation ROC-AUC of 0.9437 and a test ROC-AUC of 0.9687, along with 97% precision and 90% recall for Trojan detection. These results demonstrate that carefully designed static feature extraction combined with a robust ML pipeline can provide an effective, fast, and scalable solution for early stage hardware security analysis at the RTL level.