MACHINE LEARNING PERFORMANCE MODELING AND DESIGN-SPACE EXPLORATION OF CMOS AMPLIFIERS AND GILBERT-CELL MIXER

Abstract

Analog and radio-frequency integrated-circuit sizing commonly relies on repeated manual analysis and SPICE simulation. This study investigates supervised regression models as computationally efficient surrogates for estimating circuit performance from device geometry, bias settings, and passive-component values. Three CMOS circuits were examined: a common-source amplifier, a cascode amplifier, and a double-balanced Gilbert-cell down-conversion mixer. Extensive SPICE sweeps generated 40,068 labelled design samples covering ten performance metrics, including bandwidth, power consumption, voltage gain, conversion gain, intermediate-frequency output swing, and noise figure. Linear regression, random forest, gradient-boosted trees, and multilayer perceptron models were compared using identical 80/20 data partitions. After input and target standardization, the multilayer perceptron achieved R² values of at least 0.9987 with normalized RMSE below 0.8% for all targets. Surrogate inference required only microseconds per design point, substantially reducing evaluation time compared with transistor-level simulation. Feature-importance analysis revealed relevant design sensitivities, while Pareto analysis of 200,000 surrogate evaluations per circuit identified gain-bandwidth-power and gain-noise-power trade-offs. Additional tests examined split sensitivity, leave-one-region-out generalization, uncertainty estimation, and agreement between surrogate-selected Pareto candidates and transistor-level results. The study is limited to schematic-level, single-corner data without process-voltage-temperature variation, mismatch, layout parasitics, IIP3, or cross-topology transfer. The resulting datasets and benchmarks provide a reproducible basis for machine-learning-assisted analog design automation.