Aug 2026· Journal of systems architecture· Vol 177, pp. 103841· 0 citations· 67 references
Computer Science
TL;DR
This study investigates the most recent advances, trends, and design choices for Transformer inference on FPGA platforms, and performs a systematic literature review, extracting and delving into preferred techniques for implementation and optimisation.
Abstract
With the rapid and continuous growth in the incorporation of machine learning models based on the Transformer architecture, capable deployment is in high demand. In this context, capable deployment refers to operational performance aspects, e.g., throughput and latency, as well as efficiency aspects, e.g., energy consumption. When it comes to the task of inference using such models, purpose-built hardware accelerators provide a lucrative alternative to common deployment choices, such as Central Processing Units (CPUs) and Graphics Processing Units (GPUs). The Field Programmable Gate Array (FPGA) platforms category is an example of such alternative accelerators, promising implementation flexibility, energy efficiency, improved latency and suitability for on-site deployment. We investigate the most recent advances, trends, and design choices for Transformer inference on FPGA platforms. We perform a systematic literature review, extracting and delving into preferred techniques for implementation and optimisation. This study and the provided taxonomy of topics could act as a guide for researchers from the academia and industry alike.
Deep Neural Networks (DNNs) are critical to modern AI applications, yet their deployment on standard CPUs and GPUs is constrained by high power consumption and computational latency, particularly in resource-constrained edge environments. To address these limitations, this paper presents the design and implementation o...
P. V. G. K. Rao, Dudekula Raziya· 2026 International Conferenc...· 0 citations
This survey restricted the scope to FPGAs alone and organized 25 compression-hardware co-design case studies into a five-category taxonomy defined by which FPGA resources each strategy primarily reshapes, formalizing six open challenges: toolchain fragmentation, accuracy--efficiency characterization, automated mixed-pr...
Peter Forcha, H. Kajekusumadhar, Mbua Peter et al.· 0 citations
Deploying Transformer models on FPGA and System-on-Chip (SoC) platforms remains challenging due to their substantial computational complexity, large memory footprint, and high hardware resource requirements, particularly in multi-head attention and stacked encoder-decoder layers. This paper proposes a hardware-efficien...
Xuan Thao Tran, Thi Diem Tran· International Conference on...· 0 citations
This work analyzes the Vitis AI compiler and proposes an XIR-level splitting framework that generates independently compilable .xmodel fragments while preserving the context required for DPU mapping, and restores correct DPU mapping by addressing boundary-context loss and incomplete dependency collection.
Federico Buccellato, Luca Mannini, C. De Sio· WiPiEC Journal - Works in Pr...· 0 citations
In the evolving landscape of edge devices, unlocking artificial intelligence (AI) services via the cloud has consistently raised concerns related to energy consumption, latency, and privacy. Shifting these services locally onto edge devices powered by CPUs and GPUs have always been hindered by their limited storage a...
Doaa K. Hameed, Abdullah M. Zyarah· Journal of Forecasting· 0 citations
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