Automated Generation of RISC-V Extensions with Formal Correctness Guarantees

All Your Assembly Belongs to Rust: Automated Lifting for Uniform Testing and Verification

This paper translates Rust code containing RISC-V inline assembly into pure Rust code by emulating each instruction using a machine model extracted from the official RISC-V Sail ISA specification, and demonstrates how each category is handled by the translation.

Quantifying the Code-Size Overhead of eBPF JIT Compilation

eBPF allows user-defined programs to safely extend Linux kernel functionality at runtime, but its final machine code comes from a compilation pipeline that differs from native targets, and how efficient that pipeline is has no clear reference point. Our work constructs one: using the standard LLVM x86 backend as an app...

Unifying eBPF across Platforms: Formal Semantics, Conformance Testing, and Specifications

This work is building an executable formal semantics for eBPF in F* that explicitly distinguishes cross-platform and platform-specific behaviors and envision this semantics as a practical foundation for a uniform, trustworthy eBPF across platforms.

A Compilation-based Under-Constrained Execution Engine

PerfReasoning: How Well Do LLMs Reason on Hardware Performance?

PerfReasoning is introduced, a benchmark that evaluates LLMs both as direct performance reasoners and as generators of analytical performance-model code, exposing the gap between plausible architectural reasoning and reliable performance-model construction.

Robustness of LLM-Generated SystemVerilog Assertions to Semantics-Preserving RTL Transformations

The results show that point accuracy alone is insufficient for characterizing LLM reliability in assertion generation and motivate robustness-aware evaluation for AI-assisted hardware verification.