Bern2Edge, an end-to-end framework that uses knowledge distillation to convert a pretrained teacher feed-forward network into hardware-efficient representations via Bernstein polynomial activations, is proposed, enabling interpretable inference with explicit input-space constraints.
Abstract
Deploying high-accuracy neural networks on resource-constrained edge devices remains challenging, as existing approaches treat training, compression, and hardware synthesis as separate stages, leaving a gap between software-trained models and efficient end-to-end deployment with limited support for interpretability. We propose Bern2Edge, an end-to-end framework that uses knowledge distillation to convert a pretrained teacher feed-forward network into hardware-efficient representations via Bernstein polynomial activations. This representation enables two deployment paths: (i) a high-fidelity LUT-based realization that preserves model fidelity under compression, and (ii) a symbolic rule-based representation derived from Bernstein activation geometry, enabling interpretable inference with explicit input-space constraints. The resulting BNNs achieve up to 2.12 percentage-point (pp) accuracy improvement over ReLU under identical compression constraints. At the system level, Bern2Edge achieves up to 99.8% latency reduction and 95.2% BRAM reduction relative to a W8A8 quantized teacher on an AMD Xilinx KV260 FPGA, while maintaining accuracy within 0.5 pp, and further deploys on a low-power Spartan-7 XC7S15 FPGA. The rule-based path reduces DSP usage by up to 89.0% at a cost of 1.5 pp in total accuracy.
Feather is presented, a system that reduces this overhead by compressing intermediate activations before transmission and reconstructing them before downstream layers resume execution, consistently outperforming existing compression schemes, including linear autoencoder, PCA, and SVD.
Regan McDonald, M. Rego, Ertza Warraich et al.· Conference on Applications,...· 0 citations
An in-depth survey of model compression and optimization techniques that enable the deployment of large neural networks on resource-constrained automotive platforms is provided.
A. Thirunavukkarasu, Domenik Helms, Christian Ojeda Bernal et al.· Advances in Artificial Intel...· 0 citations
A PyTorch-based, research-oriented framework is introduced that incorporates freezing and pruning mechanisms for designing and optimizing binarized neural networks and a novel pruning method that accounts for the relative importance of learned parameters across abstraction levels is proposed.
This work surveys dozens of recent works that report compression results on real hardware and extracts practical deployment guidelines from them, and deploys compact language and image models on GPU, CPU, and Raspberry Pi platforms across question answering and image segmentation.
Subhransu Das, Jiaming Cheng, Arnav Kumar et al.· 0 citations
Conventional compute-in-memory (CIM) deployment flows usually assume a fixed crossbar geometry, although DNN layers often have different channel counts and matrix shapes. The resulting shape mismatch leaves part of the array capacity unused and can increase the number of split-and-transfer operations during inference....
Kaiwen Deng, Sifan Sun, Hanjie Liu et al.· IEEE Non-Volatile Memory Sys...· 0 citations
Efficient deployment of neural-network detectors on field-programmable gate array (FPGA) accelerators depends not only on model complexity but also on compiler-visible graph structure. On deep learning processing unit (DPU) platforms, unsupported operators can fragment execution between accelerator and host execution d...
Xiang Ji, Shuai Hu, Hao-Fei Wang et al.· Electronics· 0 citations
We use cookies to run the site and, with your consent, for analytics and to show ads.
See our Cookie Policy.