An Efficient Approximate Compressor Architecture for Balanced Error Accumulation in MAC Units

Abstract

Designing energy-efficient and high-performance arithmetic hardware remains a major challenge for modern computing systems, particularly for the multipliers and compressors that dominate multiply–accumulate (MAC) workloads. This paper presents an efficient approximate compressor architecture designed to achieve balanced error accumulation in MAC units used for error-tolerant applications such as image processing and machine learning (ML). The proposed architecture selectively simplifies the compressor stages that reduce partial products of least numerical significance, while preserving exact computation for the bits that dominate accuracy, so that approximation error accumulates in a controlled and balanced manner rather than growing unpredictably across operand widths. Building on this compressor, a configurable multiply–accumulate (MAC) unit for ML hardware is developed, capable of switching between an exact mode and 2-bit and 4-bit approximate compression modes at runtime according to instantaneous power and accuracy requirements. A modified, error-compensated activation function is further proposed to offset the systematic bias introduced by the approximate compressor at the neuron output. The proposed architecture is implemented in SystemVerilog and synthesized with Synopsys Design Compiler for UMC 90 nm CMOS technology, with functional validation on FPGA platforms. A Gaussian blur filter is used to evaluate the compressor in an image-processing pipeline, while a multilayer perceptron (MLP) trained on standard ML datasets evaluates the configurable MAC unit and the compensated activation function. Experimental results show that the proposed approximate compressor architecture achieves substantial reductions in power, area, and energy per operation relative to an exact Wallace-tree baseline, while keeping error metrics such as NMED, MRED, and ER low and well balanced across configurations, making it a strong candidate for energy-constrained, error-tolerant computing systems