DESIGN AND IMPLEMENTATION OF LOW POWER AND HIGHSPEED MULTIPLIER USING QUATERNARY CARRY LOOKAHEAD ADDER

Abstract

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high-speed DSP applications. Vedic multiplier is one of the fastest and efficient multipliers, Main algorithm of Vedic multiplication is Urdhva Triyakbhyam. It is a general multiplication formula applicable to all cases of multiplication. It literally means Vertically and Crosswise. The multiplication is depending upon the previous computations of partial sum to produce the final output, so we need to design efficient adders. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. Designing the adder using QSD number representation allows fast addition which is capable of carry free addition because the carry propagation chain is eliminated, hence it reduces the propagation time in comparison with radix 2 system. In this project, a Vedic multiplier using Quaternary Carry Look Ahead Adder (QCLA) is existed design and Vedic multiplier using Quaternary Carry Increment Adder (QCIA) is proposed design, it has less area compared with the Existed design. In this project Xilinx-ISE 14.7 tool is used for simulation, logical verification, and further synthesizing and the HDL language used for the project is VERILOG.