Novel Multiplier-Optimised Real-Time Radix-4 IFFT Architecture for High-Throughput, Low-Latency Optical OFDM Transceivers on FPGA

Abstract

Hermitian symmetry constrained optical OFDM in IM/DD transmitters incurs higher computational costs per transmitted bit than conventional complex-valued OFDM, as only a small subset of the IFFT subcarriers carry independent information. This work introduces a unified optimisation framework that combines juxtaposed IFFT architectures, arithmetic rearrangement for complex multiplication, and a novel deterministic radix-4 pruning strategy tailored for specific optical OFDM modulation formats. The proposed approach achieves higher numerical precision than comparable radix- 2 implementations, operates with up to a twofold reduction in clock cycles, and requires $\mathbf{2 5 \%-5 0 \%}$ fewer multiplications relative to the current state of art. The architecture is validated on an RFSoC $4 \times 2$ platform using a fully parallel, unrolled $N=64$ implementation. A maximum operating fabric clock of 153.6 MHz was achieved, corresponding to a throughput of 19.6608 GS/s and a latency of 19.5312 ns, while consuming only 7200 FPGA LUTs and 168 DSP slices. These characteristics make the proposed architecture well suited to low-power, low-latency, and low-complexity optical transceivers.