Lightweight Cache Buffer Management and Data Allocation Strategy for Enhancing Read/Write Latency in SSDs

Abstract

Flash memory, characterized by its rapid read and write capabilities and compact size compared to traditional hard disk drives (HDDs), has become a dominant choice for modern storage devices, particularly solid-state drives (SSDs). Despite its advantages, flash memory suffers from device wear caused by repeated write and erase operations, which increases the probability of read errors and ultimately limits SSD lifespan. To enhance SSD reliability and performance without incurring significant resource overhead, prior research has explored data allocation strategies that place frequently accessed data into lower-latency flash locations. However, such schemes typically rely on per-page access counters or LRU-based buffer management, both of which introduce non-negligible metadata maintenance overhead on resource-constrained SSD controllers. This paper introduces a Lightweight Cache Buffer Management (LCBM) strategy that avoids precise frequency tracking altogether. LCBM combines a batch-based first-in-first-out (FIFO) buffer policy with a simple swapping mechanism that dynamically adjusts data placement across the least significant bit (LSB), central significant bit (CSB), and most significant bit (MSB) positions, keeping frequently accessed data in cells with shorter read latency while fully exploiting multi-plane and intra-channel parallelism. Trace-driven simulation shows that, relative to the state-of-the-art FSPDA, LCBM reduces the average read latency by 13.62% and the write response time by 66.81% (and by 16.82% and 64.97%, respectively, over OSPADA), while eliminating the metadata overhead of counter- and LRU-based designs. We further validate LCBM at the system level on the FEMU emulator using both Filebench workloads and real-user traces, where it sustains competitive-to-higher throughput under realistic, long-term deployment scenarios.