The system advances prior physical Turing Machine demonstrations through autonomous execution, reprogrammable optical input, and quantitative evaluation of its mechanical, optical, and computational performance.
Abstract
Physical implementations of Turing Machines remain rare, and existing electromechanical demonstrators and mechanical logic games typically require manual operator intervention, either to trigger each computational step or to reconfigure the state table, or both. This restricts prior physical models to short, operator-paced demonstrations and prevents autonomous execution of extended computations. This paper addresses that gap with a hardware Turing Machine that enables autonomous multi-step execution and reprogrammable optical input without manual intervention between programs. The system integrates an Arduino Mega for state-transition logic, dual NEMA 17 stepper motors for bidirectional tape actuation, infrared reflectance sensors for symbol detection, and an ESP32-CAM-based optical punched-card reader for automated state-table loading. Hole detection under non-uniform illumination used a Breadth-First Search flood-fill algorithm with local adaptive thresholding rather than fixed global thresholding, driven by the memory and library constraints of the ESP32-CAM's microcontroller environment; this improved card-decoding accuracy from 75% to 90% (100% with mechanical card flattening) on a 20-card test set. Mechanical evaluation showed fabrication accuracy of +/-0.15 mm, rack-and-pinion positional error below 0.3 mm across 50 trials, and voltage supply stability within +/-0.2 V under full system load. End-to-end computation was validated against a parallel software simulator (tlang), with all hardware outputs matching the simulated reference exactly across multiple test programs. The system advances prior physical Turing Machine demonstrations through autonomous execution, reprogrammable optical input, and quantitative evaluation of its mechanical, optical, and computational performance.
As quantum circuits grow beyond small toy examples, preparing them for execution on physical devices becomes increasingly complex. Design automation is therefore essential for scalable quantum computing: Compilation procedures optimize resource requirements and transform circuits to a format compatible with specific hardware; resource estimation evaluates execution cost; verification methods prove circuit correctness. However, these concepts present a steep learning curve for novices, particularly when quantum circuits are introduced through low-level textual representations. To address this, we present a block-based programming framework for quantum design automation, implemented as an extension to the Scratch programming platform. This system allows users to build quantum circuits as a sequence of blocks and embed them in classical control logic to perform evaluations, compare simulation results, and directly apply different design automation techniques. We evaluated the approach in a user study with computer science students, who completed guided exercises using the platform and provided structured feedback in the form of self-reports and short knowledge assessments. Results demonstrate strong understanding and confidence in quantum design automation concepts, suggesting that the block-based approach successfully lowers the entry barrier to quantum design automation. The implemented framework is open-source and available at https://github.com/munich-quantum-toolkit/scratch-quantum.
Autonomous systems operating in the open world require world models that are robust to uncertainty, capable of long-horizon reasoning, and able to generalize to novel scenarios. Vector Symbolic Architectures (VSA), particularly Fourier Holographic Reduced Representations (FHRR), learn robust, structured, and efficient interpretable world models for planning and control. In this work, we introduce a state-of-the-art, out-of-order vector processor to natively accelerate VSA world modeling for autonomous systems with a power envelope of less than 130 mW. We evaluate our hardware-software co-design, demonstrating a 4× reduction in energy per transition and a 2× improvement in roll-out throughput compared to GPU and CPU baselines while maintaining the model's accuracy. These gains are achieved by the vector processor's intrinsic support for element-wise unitary operations and parallel computation, which aligns perfectly with VSA algebra. By unifying a structured, generalizable world model with hardware-efficient vector processing, this work enables scalable and powerful autonomous systems.
Andrew Ding, William Youngwoo Chung, N. Bagherzadeh et al.· Proceedings of the ACM/IEEE...· 0 citations
Formal verification of highly optimized arithmetic circuits at the gate-level remains a significant challenge due to the state space explosion problem. Although Symbolic Computer Algebra (SCA) offers a scalable theoretical foundation by modeling circuits as multivariate polynomials, practical implementations frequently suffer from the explosion of the size of intermediate polynomials. State-of-the-art SCA tools typically rely on fixed heuristics and restrict their application to standard multipliers. A fixed heuristic is insufficient for structurally diverse arithmetic circuits, as it often fails to generalize across all cases. In this paper, we introduce Arisca, an open-source parameterized verification framework for \textbf{Ari}thmetic circuits using \textbf{S}ymbolic \textbf{C}omputer \textbf{A}lgebra. Arisca establishes a generalized parameter space that unifies previously isolated state-of-the-art (SOTA) techniques as specific configurations within a broader algebraic reduction theory. To fundamentally transplant and elevate previous methods, we propose several algorithmic improvements, such as an HA-preserving extraction strategy, density-based vanishing detection, and conservative polynomial size estimation. In addition, Arisca expands the verification scope to encompass general arithmetic circuits with any combination of addition and multiplication, such as multiply-accumulators and dot-product units. Extensive evaluations demonstrate that Arisca achieves SOTA performance in a comprehensive suite of multiplier benchmarks and a diverse array of practical arithmetic cases.
Current analog complexity theory, built on the General-Purpose Analog Computer (GPAC) model and polynomial ODEs, allows unbounded state variables -- an assumption that is physically unrealistic for chemical reaction networks and other laboratory-scale analog computers. We develop a bounded analog complexity theory in which all state variables remain in compact intervals and physical time (wall-clock time) is the only diverging resource. Our main technical contribution is bounded surrogate compilation, a compilation framework that transforms unbounded polynomial ODE systems into bounded ones while preserving computational limits and time-to-precision guarantees. We prove that if a system is compiled into a bounded system through our algorithm, the wall-clock time of the compiled system is polynomial in the arc length and physical time of the original system. We exhibit concrete constructions demonstrating fine-grained bounded time complexity -- a tunable polynomial-degree family, a Lambert-$W$-based system achieving $\Theta(r\log r)$ time-to-precision (where $r$ is the desired precision parameter, in nats: $|x(t)-\alpha|<e^{-r}$), and an iterated-logarithm tower realizing arbitrarily high complexity classes -- all for the task of computing the constant 1. We show that bounded GPACs are closed under exponentiation ($\alpha^\beta$) with time complexity equal to the harder input, and that the full GPAC-to-CRN compilation pipeline preserves time complexity class via a low-pass filter analysis of readout modules.
Existing robotic control frameworks often rely on complex hierarchical state machines or middleware infrastructures, which may be unsuitable for resource-constrained embedded systems and difficult to map directly to low-level code. This work presents a complete state-machine model for the reactive control layer of a differential-drive mobile robot. Although mobile-robot controllers often exhibit considerable complexity—particularly at lower levels, where numerous hardware-dependent operations occur—this work shows that a network of concurrent state machines provides a clear and lightweight method for specifying and implementing control behavior. The proposed approach decomposes the reactive controller into two concurrent extended finite-state machines (CEFSMs) responsible for locomotion and lidar operation, connected through simple and predictable protocols. This structure enables a direct mapping from model diagrams to procedural code in languages such as C++ and Lua. The method has been used extensively in an undergraduate Embedded Systems course since 2011, supporting both physical robots (Arduino-based) and their digital twins in CoppeliaSim. We also introduce a discrete control strategy that approximates continuous behavior and incorporates a simplified proportional–integral–derivative (PID) controller for pose correction. The approach reduces development effort, increases model clarity, and yields reusable code across hardware and simulation platforms. Quantitative evaluation shows that the proposed PID-based control strategy can improve positioning accuracy by up to an order of magnitude compared to a baseline on–off controller, without increasing the computational cost. In addition, the control cycle time has been significantly reduced (from 31 ms to 12 ms) in order to ensure a stable execution period; this, in turn, results in a more predictable controller output and improved trajectory consistency.
Laboratory automation accelerates discovery, yet its adoption is constrained by the high cost, proprietary design, and limited remote supervisability of commercial liquid-handling systems. This work presents RAINBOT\textsuperscript{TM}, a low-cost, openly reproducible liquid-handling robot built by converting a consumer-grade Cartesian 3D printer (Elegoo Neptune 4 Max). The printer extruder is replaced by a precision single-channel pipette actuated through the printer's own G-code-driven X--Y--Z gantry, with plunger and tip-eject motions effected by two compact linear actuators under Python control. To make experiments transparent and remotely supervisable, a browser-based digital twin is implemented to synchronise bidirectionally with the physical platform, mirroring kinematics and pipetting states in real time and exposing remote monitoring, intervention, and an emergency stop from any web browser. As a proof of concept, RAINBOT\textsuperscript{TM} performed sequential exchanges of differently coloured aqueous solutions while an integrated colour sensor quantified the resulting mixtures; measured red, yellow, and blue (RYB) responses agreed with expected mixing behaviour to within a mean absolute error of two percentage points, validating correct execution and real-time tracking. Closing the loop, the platform is coupled to the CEID\textsuperscript{TM} (Cooperative Explorer for Inverse Design) framework, which recasts experimentation from iterative manual guessing into a goal-directed inverse-design search while keeping a human in the loop. The complete hardware costs under US\$1300, which is roughly an order of magnitude below entry-level commercial handlers, thereby establishing an accessible physical--virtual framework for self-driving laboratory automation.
A USAF cadet and a Lincoln Laboratory researcher found AI chatbots can help nontechnical service members produce viable software applications for their unique problems.
