Aug 2026· International Conference on Circuit, Power and Computing Technologies· pp. 1886-1891· 0 citations· 15 references
Abstract
In an effort to mitigate processing delays and latency in the traditional edge detection in the vision based systems such as robotics and surveillance platforms, this paper attempts to introduce an FPGA-based 3×3 convolution accelerator. The proposed architecture employs a multiply-accumulate (MAC) unit and fixed-point arithmetic (8-bit) to efficiently and effectively implement convolution operations in hardware. The system design is designed in Verilog HDL and simulated to ensure that the measured performance and hardware utilization metrics have been met. The suggested accelerator has proven to be dependable in edge detection and also exhibits a tangible increase in computational efficiency over the established softwarebased methods. The study therefore seeks to cast a light on the appropriateness of FPGA-based hardware acceleration in realtime image processing in embedded vision systems.
An optimized hardware implementation of fundamental image processing algorithms including Sobel edge detection, Thresholding contrast stretching and negative transformation using VHDL on FPGA architecture using VHDL is presented.
Pramod Moud, P. Sharma· International Journal of Lat...· 0 citations
Real-time image segmentation is essential for edge-based intelligent systems. Deep learning models are efficient for image segmentation compared to conventional techniques. Among other deep neural networks (DNN), MobileNet convolution neural network (CNN) model utilizes depthwise separable convolutions to reduce comput...
Shreyas V, Sinchana P. Shetty, Sripriya B. S. et al.· International Conference on...· 0 citations
A hardware-efficient object detection accelerator based on XNOR-driven variable-precision computation for real-time edge artificial intelligence that reduces arithmetic complexity, memory bandwidth, and power consumption while supporting scalable real-time object detection on FPGA-based edge platforms.
Javeed Md, Srinivasa Reddy Dumpa, K. Saisri et al.· Adolescência e Saúde· 0 citations
CNN inference on edge hardware is constrained by memory bandwidth, redundant logic, and the area overhead of fully parallel multiply-accumulate (MAC) units. This paper presents a hardware-efficient CNN accelerator with an SRAM-based architecture optimised for classifying 28×28 grayscale images. Input images are ingeste...
Avinash Krishna Pk, R. S· International Conference Inn...· 0 citations
This paper presents an FPGA feasibility study of two digital processing blocks for a future real-time Visible Light Positioning (VLP) receiver: a Sliding Discrete Fourier Transform (SDFT) stage for carrier-magnitude extraction and a hardware-optimized Multi-Layer Perceptron (MLP) inference engine for coordinate estimat...
Randy Lozada Domínguez, Aran White, Jianming Tang et al.· Electronics· 0 citations
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