Aug 2026· Proceedings of the ACM SIGCOMM 2026 Conference· 0 citations· 16 references
TL;DR
LST-Sim is presented, an efficient simulator designed for large-scale model training, balancing simulation accuracy and runtime efficiency, and a domain-based traffic management mechanism that integrates theoretical analysis with network simulation to handle different types of communication traffic, thereby improving simulation efficiency.
Abstract
Existing model training simulators fail to support heterogeneous GPU architectures and various intra-server high-speed interconnect protocols (e.g., NVLink, HCCS), while suffering from low efficiency in full-packet-level network simulation. In this paper, we present LST-Sim, an efficient simulator designed for large-scale model training, balancing simulation accuracy and runtime efficiency. First, the simulator takes into account the impacts of computational heterogeneity across different GPU models and inter-GPU interconnection bandwidth on training latency, and constructs a theoretical model. Furthermore, we propose a domain-based traffic management mechanism that integrates theoretical analysis with network simulation to handle different types of communication traffic, thereby improving simulation efficiency. The effectiveness of LST-Sim is well validated on the Ascend 910B training cluster. Its simulation results are in close agreement with real-world measurements. Meanwhile, the domain-based traffic management mechanism significantly reduces simulation runtime by approximately 75% while maintaining high fidelity.
Traditional system simulation suffers from issues such as tight coupling between models and platforms, limited local computing power, and the inability to scale external computing resources. In large-scale scenarios, simulation efficiency is low, making it difficult to achieve faster-than-real-time rapid iteration. This paper proposes a Modelasa Service (MaaS)-based faster-than-real-time simulation method oriented toward cluster computing. By decoupling and encapsulating equipment models as independent services, the method leverages distributed parallel computing on a cluster to improve per-cycle computation efficiency, thereby breaking through the performance bottleneck of traditional centralized simulation. To address the temporal inconsistency caused by asynchronous computation of model services, a barrier synchronization mechanism is introduced, ensuring that all models complete their computation and return results for the current cycle before proceeding to the next simulation cycle, thus maintaining temporal consistency throughout the simulation. Experimental results demonstrate that the proposed method can effectively scale simulation computing power and achieve simulation acceleration while ensuring temporal consistency, making it suitable for large-scale system-of-systems simulation scenarios.
Fei Guo, F. Yao, Jinpeng Zhou et al.· 2026 IEEE 27th China Confere...· 0 citations
Quanta is presented, a redundancy-aware simulation framework that eliminates repeated execution in packet-level simulation and reduces the dependence of simulation cost on physical network scale.
Jiajun Luan, Hao Li, Yihan Dang et al.· Asia-Pacific Workshop on Net...· 0 citations
High-fidelity performance simulators are essential for designing and configuring efficient AI systems, yet today's tools lack the ability to predict power consumption. Established GPU power models rely on hardware utilization counters, which do not exist until the workload has actually run. This work evaluates whether Model FLOPs Utilization (MFU)-an analytical, software-defined metric relating achieved throughput to peak hardware capability-can serve as a portable, software-defined predictor of GPU power for LLMs. We benchmark almost 3000 single-device training runs across six GPUs, covering different model families, numerical precisions, batch sizes, and context-window lengths. We find that a linear MFU-based power model fits every tested GPU as long as the workload is compute-bound, as in production LLM training. Fitting per-(GPU, dtype, batch size) instead of per-GPU drops the within-cell mean error from around 10% to around 1%, matching the cross-repeat measurement-noise floor.
Splitting complex model inference between multiple computing devices can overcome latency and energy constraints at the edge. Newer edge accelerator devices with higher computing capacity and energy efficiency, enable more fine-grained offload throughout layers of the network, leading to the potential for multiple split configurations. However, optimizing a DNN for inference across networked devices requires a precise performance model that can guide design choices. In this paper, we demonstrate that existing models for computation and communication latency are inaccurate due to system considerations and propose a new empirical model based on structured benchmarking, considering data ingestion overhead due to transfers between devices as well as within a device for data to reach the GPU. We validate our split inference performance model using VGG16 and ResNet50 networks on two heterogeneous platforms, showing it achieves a mean absolute error of no more than 4% for both DNNs, significantly outperforming previous models with errors of more than 15%. We also validate the practical utility of our model by incorporating it into existing split inference search algorithms under multi-split, dynamic bandwidth, and multi-tenant scenarios, demonstrating its effectiveness in navigating the split inference search space.
Hao Liu, M. Fouda, Ahmed M. Eltawil et al.· International Conference on...· 0 citations
We present SimDSL, a domain-specific language (DSL) for executing large-scale simulations on the GPU using an Entity Component System (ECS) architecture. Systems written in SimDSL are analyzed, lowered into an intermediate representation, and compiled by a CuPy-based backend into CUDA kernels operating over structure-of-arrays archetype tables. We evaluate SimDSL on five workloads: Particle Fountain, Traffic Ring, Reaction Diffusion, Ant Colony, and Tower Defense. The evaluation compares SimDSL with straightforward CuPy and CUDA baseline implementations under matched simulation configurations. Results show that SimDSL sustains GPU-resident execution and achieves favorable performance relative to these baselines. These findings demonstrate that high-level ECS simulation programs can be compiled into efficient GPU execution without requiring users to manually implement and coordinate low-level kernels.
Network simulation plays a critical role in improving the efficiency of large-scale AI clusters for design validation, parameter tuning, and protocol development. However, high-fidelity network simulation becomes prohibitively slow at scale, especially when running large batches of experiments on topologies with tens or hundreds of thousands of accelerators. We observe that a key bottleneck comes from the control plane. Existing network simulators typically compute routes and install forwarding tables at initialization, which can consume hundreds of GB of memory before packet-event execution begins and limit overall simulation throughput. In this paper, we present Nüwa, which views routing as a compilation problem, it leverages the hierarchical and symmetric structure common in AI fabrics and compiles a declarative topology description together with routing policies into compact forwarding artifacts that are fast to generate and efficient to look up. Evaluations show that Nüwa can reduce simulation initialization time from hours to only 25 seconds for a 65,536-GPU cluster. For end-to-end simulation time, Nüwa takes only 20% of that required by existing approaches in a 40K+ GPU cluster, and Nüwa can scale to a 221,184-GPU cluster.
Wenkai Li, Ran Shu, Peng Zhang et al.· Proceedings of the ACM SIGCO...· 0 citations