TL;DR
A hardware algorithm co-optimization framework for high-throughput deployment of deep object detection models on reconfigurable architectures, demonstrating the effectiveness of algorithm architecture co-design in overcoming memory and parallel efficiency bottlenecks and providing a practical solution for real-time high-performance deployment of deep learning models.
A systematic review of FPGA-based DL deployment from a cross-layer perspective spanning model, compiler, architecture, runtime, and electronic design automation (EDA) is presented, highlighting that reliable cross-study comparison requires careful consideration of model configuration, precision, execution phase, batch...
To address the challenges of deploying deep neural networks (DNNs) on heterogeneous edge platforms for industrial defect detection, this study optimizes the YOLOv8n model for the RISC-V K230 platform. Microbenchmarking and pipeline analysis reveal three primary bottlenecks impeding lightweight deployment: memory bandwi...
Low-level hardware acceleration strategies to deconstruct the mapping from algorithm logic to silicon substrates are reviewed to provide strong guidelines for the hardware-software co-design of emerging ultra-low power edge Artificial Intelligence (AI) chips.
Traffic object detection for deployment is constrained by accuracy, latency, model size, and computational cost. Under a unified dataset, deployment pipeline, and single-GPU hardware platform (RTX 4090), this paper evaluates the combined effects of structured pruning and low-precision inference. Using YOLOv5s as the pr...
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