NEMO is presented, a nimble and expressive hardware memory telemetry engine for server memory controllers (MCs) that gives OS subsystems policy-specific views of memory behavior and provides higher-fidelity signals at substantially lower CPU overhead across a range of state-of-the-art memory management systems.
CAISA is introduced, a composable AI systems architecture that enables disaggregated memory expansion for large-scale AI workloads using CXL-based shared memory and coupling memory isolation with software-managed data orchestration decouples compute and memory resources while preserving efficient data movement, providi...
Divya Kiran Kadiyala, Lianjie Cao, Jinsun Yoo et al.· Conference on Applications,...· 0 citations
CXL-enabled memory expands server memory capacity, but introduces a page-placement problem: the operating system must decide which pages should reside in DRAM and which should reside on slower CXL memory. Existing systems make this tradeoff in one of two ways. Userspace controllers support flexible policies, but expose...
Results show that standardizing the host-interface layer reduces both the engineering cost of PIM simulator development and the energy overhead of simulation-driven workload evaluation, while reducing host CPU utilization and package energy by up to 50% on transfer-intensive workloads.
SolidAttention is introduced, an LLM inference engine which addresses limitations through a tight co-design of dynamic attention sparsity algorithms and SSD-based storage management and minimizes SSD-induced blocking latency.
Xin Zheng, Dong-Liang Wei, Jian-Xiang Gao et al.· 0 citations
Preliminary but compelling evidence that MC-aware scheduling is a practical operating system/runtime direction for deployable embodied AI on unified memory edge devices is provided.
Teng Mei, Cheng-Xuan Pei, Marco Canini et al.· Proceedings of the 17th ACM...· 1 citation
Dorado is a novel design that scales SmartNIC session tables entirely on inexpensive DDR modules and uses three new techniques that extract commodity DDR performance by restructuring session table layout, decomposing processing pipelines to reduce locking, and scheduling memory accesses to minimize stalls.
Heng Yu, Kai Ren, Jiajun Liang et al.· Conference on Applications,...· 0 citations
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