Skip to content
Open access

A HYBRID MITIGATION STRATEGY FOR SIDE-CHANNEL ATTACKS ON ARM CORTEX-M MICROCONTROLLERS

Aug 2026 · Revista de Estudos Interdisciplinares · Vol 25, pp. e3546 · 0 citations

TL;DR

This research proposes the development and validation of a software-based hybrid mitigation strategy for side-channel attacks on ARM Cortex-M microcontrollers, using the NUCLEO-H753ZI board, to contribute to improved security in low-cost embedded systems.

Abstract

This research proposes the development and validation of a software-based hybrid mitigation strategy for side-channel attacks on ARM Cortex-M microcontrollers, using the NUCLEO-H753ZI board. Side-channel attacks exploit non-functional physical information such as power consumption, execution time, and electromagnetic emissions to extract sensitive data, including cryptographic keys. The study is motivated by the increasing adoption of low-cost embedded systems in critical applications (e.g., medical devices, home automation, and industrial systems); these systems face processing, memory, and power constraints that hinder the implementation of advanced security mechanisms. Although software and hardware countermeasures exist to reduce the effectiveness of these attacks, many require resources incompatible with lower-capacity devices. The proposed methodology will leverage integrated features of the NUCLEO-H753ZI platform such as the random number generator (RNG) and hardware cryptographic accelerators combined with techniques including noise insertion, temporal jitter, execution shuffling, and dummy operations. These countermeasures will be applied to AES and RSA algorithm implementations to enhance their resistance against SPA and DPA attacks. Validation will be conducted through power consumption measurements using laboratory instruments, comparing scenarios with and without the mitigation techniques. The study aims to demonstrate that the hybrid strategy reduces the exposure of signals exploitable by side-channel attacks without significantly compromising performance or energy consumption, thereby contributing to improved security in low-cost embedded systems.

Read PDF

Similar papers

Review Open access 2026

Analysis of Countermeasures Techniques Against Side-Channel Attacks on Electronic Circuits: A Review

Side-channel attacks (SCAs) exploit unintended physical leakages in digital systems, such as power consumption, electromagnetic emissions, and execution time, to extract sensitive information, including cryptographic keys. This article presents a comprehensive comparative study of several families of countermeasures, i...

Yahaya Coulibaly, Ousmane Traoré, Daouda Traoré · 0 citations
Open access Sep 2026

EVALUATING THE EFFECTIVENESS OF ALGORITHMIC NOISE REDUCTION IN POWER SIDE-CHANNEL ATTACKS ON AN FPGA-BASED CGRA CRYPTOGRAPHIC ACCELERATOR SUPPORTING MULTI-TASK AES-128

Power side-channel attacks represent a serious threat to cryptographic accelerators implemented in hardware. This article experimentally evaluates the power side-channel vulnerability of LiCryptor, a CGRA-based cryptographic accelerator, when executing AES-128 in a pipelined, multi-threaded configuration supporting 16...

Van-Tuan Luu · 0 citations
Open access Sep 2026

Power Analysis and Countermeasures on the MiMC Block Cipher

Modern zero-knowledge (ZK), fully homomorphic encryption (FHE) and Multi-party Computation (MPC) protocols have motivated research interest in Arithmetization-Oriented (AO) cryptographic primitives. The use of these protocols on embedded platforms requires consideration for protection against side-channel analysis (SCA...

E. Andreeva, Stefan Mangard, Rishub Nagpal et al. · 0 citations
Open access Aug 2026

Design methodology of clock signal manipulation detectors in FPGAs and ASICs to strengthen vulnerable cryptosystems against fault injection

This paper presents a methodology for designing a lightweight detection scheme for detecting fault injections by clock manipulation in hardware-oriented information encryption algorithms in both FPGAs and ASICs and shows that the scheme is able to detect 100% of both the clock signal manipulation and electromagnetic at...

F. E. Potestad-Ordóñez, E. Tena-Sánchez, J. M. Mora-Gutiérrez et al. · 0 citations
Open access 2026

Revisiting Side-Channel Resistance of GCM Implementations on AVR Microcontrollers

Galois/Counter Mode (GCM) serves as a mandatory or default authenticated encryption mode in widely deployed security protocols, including TLS 1.3, IPsec, MACsec (IEEE 802.1AE), SSH, WPA3, and QUIC, which makes implementation-level vulnerabilities in GCM a concern of broad practical significance. In this study, we revis...

Insung Kim, Hanbeom Shin, Sunyeop Kim et al. · 0 citations

We use cookies to run the site and, with your consent, for analytics and to show ads. See our Cookie Policy.