Open access
2026
Design of a 1-bit Adder/Subtractor Using Multi-Gate Transistors for High Speed and Low Power Applications
The results establish the feasibility of the proposed MGFET-based programmable logic architecture for compact, high-speed, and low-power arithmetic circuits for future programmable nanoscale digital systems.
A. Sinha, S. L. Sangam
· IEEE Access · 0 citations