Design of a 1-bit Adder/Subtractor Using Multi-Gate Transistors for High Speed and Low Power Applications
TL;DR
The results establish the feasibility of the proposed MGFET-based programmable logic architecture for compact, high-speed, and low-power arithmetic circuits for future programmable nanoscale digital systems.
Abstract
Compact and energy-efficient adder and subtractor circuits are the basic building blocks of the arithmetic circuits. This work presents the conceptual design of a 1-bit adder/subtractor using four Functionally Programable Logic cells (FPLCs). Each FPLC is realized using non aligned multi-gate field-effect transistors (MGFETs) operating in short-gate and independent-gate modes. The proposed non aligned MGFET device is of 50 nm channel length, and uses uniform gate oxide and a single metal work function. The proposed FPLC, enables the realization of universal logic functions (NAND and NOR) as well as exclusive logic functions (XOR and XNOR) through bias-controlled functional programmability, without requiring any modification to the device’s physical geometry or material parameters. At 0.95 V supply, 1.0 GHz input frequency, and 10 fF load, the FPLCs based NAND, NOR, XOR, and XNOR gate response a propagation delay of 6.9 ps, 5.2 ps, 5.4 ps, and 6.1 ps, respectively. A 1-bit adder/subtractor designed by using four FPLCs works with a propagation delay of 13.98 ps (sum), 10.10 ps (carry), 13.87 ps (difference), and 8.48 ps (borrow). Parametric analyses considering process and operating variations further demonstrate stable circuit functionality and predictable delay characteristics. These results establish the feasibility of the proposed MGFET-based programmable logic architecture for compact, high-speed, and low-power arithmetic circuits for future programmable nanoscale digital systems.