Design and Analysis of a Low-Power Hybrid 10-Transistor CMOS Full Adder in 180 nm Technology

Abstract

This paper presents the design, comparative analysis, and simulation of a low-power hybrid 10-transistor (10T) CMOS full adder realized in a 180 nm technology with a 1.8 V supply. The proposed cell combines a six-transistor XOR/XNOR module with a two-transistor pass-transistor carry network and a two-transistor transmission-gate sum multiplexer, achieving full output swing and balanced rise/fall behaviour while eliminating the stacked contention paths of conventional static CMOS. An exhaustive simulation campaign over the eight-input truth-table space at 100 MHz with a 10 fF load demonstrates that the proposed adder consumes 2.67 μW, exhibits propagation delays of 322.7 ps and 207.5 ps for the sum and carry outputs, and attains a power-delay product of 861.6 fJ. Relative to the conventional 28-transistor static CMOS adder, these figures correspond to savings of 63.5% in power, 65.1% in sum delay, and 87.3% in power-delay product, while transistor count falls from 28 to 10. A supply-voltage sweep from 1.2 V to 2.0 V confirms correct functionality down to 1.2 V with quadratic dynamic-power scaling, and the pass-transistor critical path remains functional across process corners. The findings indicate that topology-driven minimisation of switched capacitance and internal node count, rather than device-level tuning alone, is the dominant lever for energy-efficient arithmetic in portable and embedded applications.