Soniya Patel, Deepali Sahu, Madhu Vishwakarma

Design and Analysis of a Low-Power Hybrid 10-Transistor CMOS Full Adder in 180 nm Technology

This paper presents the design, comparative analysis, and simulation of a low-power hybrid 10-transistor (10T) CMOS full adder realized in a 180 nm technology with a 1.8 V supply. The proposed cell combines a six-transistor XOR/XNOR module with a two-transistor pass-transistor carry network and a two-transistor transmi...