Author

Amir Hossein Jalilvand

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Preprint Aug 2026

A Low-Latency ASIC Architecture for Real-Time Line Segment Detection

The proposed design is based on the step-length algorithm and incorporates five ASIC-specific features: register-based line buffering with data reuse, multiplierless MCM-based filtering, 8-class angle quantization, a CAM-like associative memory for single-cycle matching, and an optimized duplicate removal mechanism.

Amir Hossein Jalilvand, P. Panahi, M. Najafi · 2 citations

Review Aug 2026

Hardware-Enabled Fuzzy Inference: Architectures, Platforms, and Emerging Trends

This survey presents the first comprehensive, platform-centric review of hardware fuzzy systems, systematically organizing the literature into three principal categories: FPGA-based implementations, ASIC and custom VLSI realizations, and embedded, IoT, and TinyML platforms.

Amir Hossein Jalilvand, P. Panahi, M. Najafi · 0 citations