Aug 2026
BREEZE: a binary pattern encoded edge accelerator for spatio-temporal sparse delta LSTMs on FPGAs
BREEZE is proposed, a novel configurable hardware accelerator featuring a hardware-coupled Binary Pattern Encoding (BPE) scheme and a row-wise execution architecture that achieves throughput comparable to state-of-the-art implementations while reducing LUT utilization by up to 25.6%.
Atefeh Samadi-Meibodi, B. Alizadeh
· Journal of Supercomputing · 0 citations