TL;DR
BREEZE is proposed, a novel configurable hardware accelerator featuring a hardware-coupled Binary Pattern Encoding (BPE) scheme and a row-wise execution architecture that achieves throughput comparable to state-of-the-art implementations while reducing LUT utilization by up to 25.6%.
Machine learning inference is moving to the edge due to latency, energy, and privacy constraints. The growing complexity of edge workloads places increasing pressure on memory hierarchies, making data movement a major limitation for both performance and energy efficiency. Fixed-function accelerators inherit the memory...
In the evolving landscape of edge devices, unlocking artificial intelligence (AI) services via the cloud has consistently raised concerns related to energy consumption, latency, and privacy. Shifting these services locally onto edge devices powered by CPUs and GPUs have always been hindered by their limited storage a...
Long Short-Term Memory (LSTM) networks continue to be widely deployed for real-time sequential tasks on edge devices, yet their computational demands challenge deployment on resource-constrained hardware. This work introduces COBALT, a bit-serial compressed LSTM accelerator built on a matrix (input)-vector (weight) ref...
This review surveys the full landscape of AI hardware accelerators for LLMs, including general-purpose GPUs, custom ASICs, reconfigurable FPGAs, processing-in-memory and near-memory architectures, and emerging neuromorphic and photonic approaches across cloud and edge deployment.
DCSR-GCN, a high-performance GCN accelerator based on dynamic compression and sparsity reordering based on dynamic compression and sparsity reordering, is presented and a two-phase reordering algorithm that combines conflict-aware row scheduling with reuse-aware column grouping is proposed, thereby mitigating RAW confl...
A memory-efficient hardware accelerator for depthwise separable convolution that minimizes off-chip memory traffic and parameter storage and performs the depthwise separable convolution with a small number of logic resources and on-chip memory, confirming its feasibility for resource-constrained edge devices.
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