Data movement has become a dominant bottleneck in modern artificial intelligence hardware, making in-memory computing a critical direction for energy-efficient and memory-centric architectures. Ferroelectric hafnium oxide provides a distinctive materials platform for this transition because field-driven polarization switching, non-volatility, CMOS compatibility, and nanoscale thickness scalability can be combined within a process-relevant oxide system. This review establishes a device-to-system perspective on HfO2-based and Hf0.5Zr0.5O2-based ferroelectric memories for in-memory computing. Instead of treating ferroelectric materials, memory devices, circuit primitives, and computing architectures as separate research topics, we examine how their mutual constraints define the achievable efficiency, precision, reliability, and scalability of hafnia-based computing systems. The discussion connects polarization engineering and defect control with charge-domain computation, threshold-state logic, associative search, analog weight representation, neuromorphic plasticity, and sensor-side processing. Particular emphasis is placed on the translation of ferroelectric functionality from individual devices to arrays, macros, and system-level accelerators. We identify variability, fatigue, charge trapping, multilevel-state uncertainty, peripheral overhead, and benchmarking inconsistency as the central barriers that prevent device-level advantages from directly becoming system-level gains. Finally, we outline a cross-layer roadmap in which ferroelectric stack engineering, variability-tolerant arrays, precision-scalable architectures, and SoC-level integration are co-optimized to enable reliable HZO-based memory-centric computing.
Chen He, Wei Li, Jianjun Li et al.· Micromachines· 0 citations
The conventional von Neumann architecture, constrained by the memory and power walls arising from the separation of storage and computation, faces significant limitations in computational efficiency and energy consumption. To address these challenges, this paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array. The proposed architecture performs majority-based bitwise computation by simultaneously activating multiple word lines, enabling AND and OR operations in conventional 2T-2C FRAM cells. Selectively embedded 4T-2C FRAM cells further provide in-array inversion, extending the supported functions to NOT and functionally complete Boolean logic. The architecture also supports full-adder operations and stores input operands, intermediate data, and output results within the same FRAM subarray, thereby reducing data movement. Moreover, the architecture provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption. The internal computation, nevertheless, relies on analog charge sharing and differential sense-amplifier resolution. HSPICE simulations indicate PVT-evaluated sensing stability and computational efficiency under the evaluated conditions. The bit-line voltage difference reaches 337 mV under triple-row activation and 214 mV under quintuple-row activation, with the former being 5.2 times that of the reported DRAM implementation used for comparison. At 3.3 V, process–voltage–temperature (PVT) simulations show that the maximum deviation of ΔV from its mean value remains below 4.62% across the evaluated process corners and temperatures from −40 °C to 125 °C. Simulations of the 8 × 8 FRAM CiM compute-array circuit model yield an energy consumption of 1.94–3.46 pJ/bit and a calculation latency of 0.599–1.167 ns for the supported bitwise operations, corresponding to a 4.86×–5.90× reduction in energy consumption compared with the reported DDR3-based design. The architecture also supports parallel processing and mitigates data loss associated with destructive FRAM readout through an in-array replication mechanism. Finally, an 8 × 8 hybrid FRAM CiM prototype was fabricated in a 180 nm CMOS process as a physical implementation of the proposed hybrid architecture, and its basic array functionality was verified.
Chen He, Jianjun Li, Wei Li et al.· Electronics· 0 citations
To address the “memory wall” bottleneck in von Neumann architectures, this paper proposes novel FeFET-embedded Complementary Metal-Oxide-Semiconductor (CMOS) adders for efficient Processing-in-Memory (PiM). Leveraging the tunable threshold voltage of Ferroelectric Field-Effect Transistors (FeFETs), the design enables Analog-to-Digital Converter (ADC)-free arithmetic operations by integrating data storage and logic within a hybrid circuit structure. We detail the implementation of FeFET-embedded NOT-AND (NAND) and Exclusive OR (XOR) gates to construct half-adders, full-adders, and a scalable 4-bit adder. Operating in distinct write and calculation modes, the architecture performs in-memory addition without complex signal converters. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations validate the functional correctness, low energy consumption and low latency of the proposed design. The proposed FeFET-PiM adder achieves an ultra-low computational energy consumption of 0.657 fJ/bit and a latency of merely 48.6 ps. These figures represent a significant reduction compared to analog PiM adders, demonstrating its substantial potential for low-power advanced electronic devices.
Chen He, Wei Li, Jianjun Li et al.· Journal of Physics, Conferen...· 0 citations