FeFET-embedded CMOS Circuit Design for Processing-in-memory Adder

Abstract

To address the “memory wall” bottleneck in von Neumann architectures, this paper proposes novel FeFET-embedded Complementary Metal-Oxide-Semiconductor (CMOS) adders for efficient Processing-in-Memory (PiM). Leveraging the tunable threshold voltage of Ferroelectric Field-Effect Transistors (FeFETs), the design enables Analog-to-Digital Converter (ADC)-free arithmetic operations by integrating data storage and logic within a hybrid circuit structure. We detail the implementation of FeFET-embedded NOT-AND (NAND) and Exclusive OR (XOR) gates to construct half-adders, full-adders, and a scalable 4-bit adder. Operating in distinct write and calculation modes, the architecture performs in-memory addition without complex signal converters. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations validate the functional correctness, low energy consumption and low latency of the proposed design. The proposed FeFET-PiM adder achieves an ultra-low computational energy consumption of 0.657 fJ/bit and a latency of merely 48.6 ps. These figures represent a significant reduction compared to analog PiM adders, demonstrating its substantial potential for low-power advanced electronic devices.