Dr. Javeed MD, Dr. Radha Krishna A.N, K Parameshwa

Scalable Modified Vedic Multiplier Using HSCG-SCG-CSLA for High-Speed FPGA Arithmetic

High-speed multiplication is a dominant requirement in digital signal processing, image processing, cryptography, and embedded arithmetic units. This work develops a scalable modified Vedic multiplier based on the Urdhva-Tiryagbhyam vertical-and-crosswise principle and replaces conventional carry-intensive final additi...