Scalable Modified Vedic Multiplier Using HSCG-SCG-CSLA for High-Speed FPGA Arithmetic

Abstract

High-speed multiplication is a dominant requirement in digital signal processing, image processing, cryptography, and embedded arithmetic units. This work develops a scalable modified Vedic multiplier based on the Urdhva-Tiryagbhyam vertical-and-crosswise principle and replaces conventional carry-intensive final addition with a modified Half Sum Carry Generation–Sum Carry Generation Carry Select Adder (HSCG-SCG-CSLA). The architecture is constructed hierarchically from small Vedic cells, aligned partial products, and a decoder-assisted carry generation network. The design is described in Verilog HDL and evaluated using the Vivado simulation and synthesis flow for 4-, 8-, 16-, 32-, and 64-bit operands. The supplied implementation data show consistent LUT reduction for the multiplier family, including 20 versus 22 LUTs at 4 bits, 472 versus 482 LUTs at 16 bits, and 8147 versus 8311 LUTs at 64 bits. The delay result is most significant at 64 bits, where the proposed architecture reports 2.0371 ns compared with 3.6635 ns for the decoder-based Vedic baseline, corresponding to a 44.4% reduction. At 16 bits, delay decreases from 3.0507 ns to 2.8432 ns and total power from 45.541 W to 44.554 W. The results therefore indicate that the architectural benefit increases with selected word lengths, particularly when carry resolution dominates the critical path. The paper also discusses cases where the proposed structure introduces small overheads, emphasizing the importance of word-length-aware optimization