Dr. Radha Krishna A.N, Vasikarla Renuka, Vemula Vi

Resource-Efficient VHDL UART Soft Core with 16× Oversampling, Configurable Parity and Double-Buffered Data Paths for Spartan-3E FPGA

Universal Asynchronous Receiver/Transmitter (UART) remains one of the most widely used low-complexity interfaces for communication between processors, embedded controllers and external peripherals. This paper presents a modular VHDL implementation of a UART soft core intended for FPGA-based embedded systems. The archit...