Resource-Efficient VHDL UART Soft Core with 16× Oversampling, Configurable Parity and Double-Buffered Data Paths for Spartan-3E FPGA

Abstract

Universal Asynchronous Receiver/Transmitter (UART) remains one of the most widely used low-complexity interfaces for communication between processors, embedded controllers and external peripherals. This paper presents a modular VHDL implementation of a UART soft core intended for FPGA-based embedded systems. The architecture integrates a host-visible register block, baud/clock divider, parity generation and checking, a finite-state-machine-based transmitter, a receiver employing 16× oversampling and center-bit sampling, and buffered data paths for decoupling the processor interface from serial transfer. The transmitter converts an 8-bit parallel word into an asynchronous frame with start, data, optional parity and stop bits, while the receiver validates the start bit, samples the data stream near the center of each bit interval and reconstructs the parallel byte. Functional verification was carried out in ModelSim and synthesis was performed using Xilinx ISE for a Spartan-3E XC3S500E device in the FG320 package with speed grade -4. The reported implementation uses 51 of 4,656 slices, 54 slice registers, 76 four-input LUTs, 22 bonded I/O blocks and one BUFGMUX. The synthesis timing report gives a minimum period of 5.953 ns, corresponding to a maximum frequency of 167.983 MHz, with all timing constraints reported as met. The results demonstrate that the architecture provides correct serial-to-parallel and parallel-to-serial operation with low FPGA resource occupation, making it suitable as an embedded communication peripheral and as a reusable teaching or prototyping IP core.