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Hao-Zhe Huang

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Conference Open access 2026

DSP Hardware Architecture Design for Low-Latency and Ultra-Reliable Communication

A review of the DSP hardware architecture for URLLC scenarios and the collaboration of AI with DSP, terahertz processing, and 6G extreme URLLC architecture is envisioned, providing systematic technical references for researchers.

Hao-Zhe Huang · ITM Web of Conferences · 0 citations