DSP Hardware Architecture Design for Low-Latency and Ultra-Reliable Communication
TL;DR
A review of the DSP hardware architecture for URLLC scenarios and the collaboration of AI with DSP, terahertz processing, and 6G extreme URLLC architecture is envisioned, providing systematic technical references for researchers.
Abstract
Ultra-reliable low-latency communication (URLLC) is a core element of 5G and future wireless networks, and it is the core support for advanced technologies such as automation in industry and intelligent driving. These scenarios require an end-to-end time delay of less than 1 millisecond and an error rate of less than 10-9, which pose extremely high challenges to the infrastructure of communication networks and digital signal processing (DSP) hardware. This paper provides a review of the DSP hardware architecture for URLLC scenarios. Firstly, the time delay budget of the dynamic cloud radio access network is analyzed, leading to the conclusion that priority should be given to addressing the time delay issue. Secondly, the key DSP modules are studied. Furthermore, the reliable slicing technology in optical metropolitan area networks is discussed, the dedicated protection and shared protection strategies are considered, and a dynamic optimization algorithm based on backup resource reconfiguration is proposed. Finally, the collaboration of AI with DSP, terahertz processing, and 6G extreme URLLC architecture is envisioned, providing systematic technical references for researchers.