Design and Simulation of a Lightweight All-Digital Clock Recovery Algorithm for Low-Speed Optical Communications
TL;DR
A second-order all-digital phase-locked loop (ADPLL) architecture based on fixed-point Gardner timing error extraction is proposed, which employs a physical oversampling strategy to trade memory bus bandwidth for core computational power.
Abstract
Aiming at the asynchronous clock skew and computational power bottlenecks faced by resource-constrained microcontrollers in short-reach optical communications, this paper proposes a lightweight all-digital clock and data recovery (CDR) algorithm specifically designed for platforms lacking a hardware floating-point unit (FPU). Traditional hardware transceiver mechanisms are highly sensitive to sampling frequency offsets (SFO). Conversely, conventional software synchronization algorithms, while robust in degraded channels, are computationally complex and exceed the carrying capacity of low-power cores. To bridge this gap, this study proposes a second-order all-digital phase-locked loop (ADPLL) architecture based on fixed-point Gardner timing error extraction. The proposed architecture employs a physical oversampling strategy to trade memory bus bandwidth for core computational power. Simulation results demonstrate that at a baud rate of 115.2 kbps, a single closed-loop execution of the proposed algorithm consumes only about 40 processor clock cycles, maintaining a theoretical CPU load below 12.8%. Under extreme initial frequency offsets up to 5,000 ppm and Additive White Gaussian Noise (AWGN) channels, traditional hardware mechanisms fail. In stark contrast, the proposed algorithm exhibits excellent phase-tracking and noise-resilience capabilities, achieving an error-free transmission (Bit Error Rate < 10^-4) at a Signal-to-Noise Ratio (SNR) of 12 dB.