Design and analysis of an ultra-low-power dual edge-triggered D flip-flop for high-speed applications

Abstract

In contemporary very large scale integration (VLSI) designs, flip-flops consume a substantial amount of power due to the constant switching of the clock. Consequently, designing energy-saving storage devices has become necessary for both mobile and high-performance digital systems. This paper introduces an ultra-low-power dual edge-triggered D flip-flop (DETFF) design realized in 45 nm CMOS process technology. Proposed architecture uses positive and negative latches with regenerative feedback and an efficient output selection circuitry to capture data during rising and falling edges of the clock. Due to its ability to trigger on two clock edges, the design allows for achieving the same throughput at half the clock frequency in comparison with traditional single-edge-triggered flip-flops and decreases power consumption related to clock switching. Design operates at 0.5 V and 100 MHz clock frequency and has been simulated under typical–typical (TT), fast–fast, slow–slow, fast–slow, and slow–fast process corners. It is shown that the introduced DETFF consumes power 30.09 nW at the TT corner, thus providing power savings of 48.25%, 80.71%, 53.82%, 67.97%, 48.58%, and 51.22% in comparison with the C-element, STC, SDET, true-single-phase clocked-SDET, fully static true-single-phase-clocked, and LPTSPC designs, correspondingly. Moreover, proposed design provides better propagation delay performance than most of the existing solutions. The absence of floating internal nodes and use of regenerative feedback ensure higher circuit stability and noise immunity. The results confirm the suitability of the designed DETFF for low power and fast VLSI circuits.