Field-Programmable Gate Array (FPGA) synthesis and simulation tools, such as Vivado, Quartus, Yosys, and Icarus Verilog, are key components of Electronic Design Automation (EDA) toolchains, translating high-level Hardware Description Language (HDL) designs into low-level gate netlists. However, defects in these compile...
He Jiang, Wen Zhao, Shi-Kai Guo et al.· Proceedings of the ACM on So...· 0 citations
Program-level Binary Code Similarity Analysis (BCSA) aims to identify semantically similar code regions across binary programs, serving as a fundamental technique for software plagiarism detection, vulnerability search, and malware analysis. Existing approaches often decompose binaries into modules following the struct...
Ang Jia, He Jiang, Zhipeng Yang et al.· 0 citations
Results show that CoSTAR enables small, locally deployable LLMs to achieve performance competitive with substantially larger LLMs for privacy-sensitive COBOL legacy systems.
Hao-Rui Lin, He Jiang, Xiao-Chen Li et al.· 0 citations
SynaSpace is a behavior-driven configuration optimization framework for fault detection in logic synthesis tools that focuses on synthesis behavior coverage to guide configuration search, by constructing behavioral representations through joint analysis of synthesis logs and gate-level netlists.
Pei-Yu Zou, Xiao-Chen Li, Yijia Meng et al.· ACM Transactions on Design A...· 0 citations
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