Fuzzing FPGA Synthesis and Simulation Tools via LLM-Generated Syntax-Valid HDL Codes

Abstract

Field-Programmable Gate Array (FPGA) synthesis and simulation tools, such as Vivado, Quartus, Yosys, and Icarus Verilog, are key components of Electronic Design Automation (EDA) toolchains, translating high-level Hardware Description Language (HDL) designs into low-level gate netlists. However, defects in these compilers can propagate into the synthesized netlists, leading to crashes and functionally incorrect or even insecure hardware implementations and posing significant security risks. Existing fuzz testing approaches face several challenges, including limited diversity in primitive-cell types and a lack of feedback-guided exploration. These issues restrict their ability to thoroughly exercise the compilers and expose deep-seated defects. To address these challenges, we propose PolyHDL, which leverages the prompting Large Language Models (LLMs) for generating valid HDL designs to detect compiler defects in FPGA synthesis and simulation tools. By leveraging prompt learning and integrating feedback-driven guidance from primitive-cell diversity, PolyHDL generates semantically valid HDL designs with diverse primitive-cell combinations, thereby addressing the aforementioned challenges. Furthermore, through equivalence check, PolyHDL effectively reveals potential compiler defects in FPGA synthesis and simulation tools. Experimental results demonstrate that PolyHDL successfully identified and reported 18 valid defects in widely used toolchains, including Vivado, Yosys, Icarus Verilog, and Quartus within one month, 17 of which were confirmed by the official technical support, and achieved a 13.1%–13.4% improvement in code coverage over the SOTA approaches.