Wen Zhao

Fuzzing FPGA Synthesis and Simulation Tools via LLM-Generated Syntax-Valid HDL Codes

Field-Programmable Gate Array (FPGA) synthesis and simulation tools, such as Vivado, Quartus, Yosys, and Icarus Verilog, are key components of Electronic Design Automation (EDA) toolchains, translating high-level Hardware Description Language (HDL) designs into low-level gate netlists. However, defects in these compile...