Author

Xiao-Chen Li

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Open access Oct 2026

Fuzzing FPGA Synthesis and Simulation Tools via LLM-Generated Syntax-Valid HDL Codes

Field-Programmable Gate Array (FPGA) synthesis and simulation tools, such as Vivado, Quartus, Yosys, and Icarus Verilog, are key components of Electronic Design Automation (EDA) toolchains, translating high-level Hardware Description Language (HDL) designs into low-level gate netlists. However, defects in these compile...

He Jiang, Wen Zhao, Shi-Kai Guo et al. · 0 citations

#small language model Preprint Sep 2026

CoSTAR: Data Synthesis-Driven Constraint-Aware COBOL Section Summarization for Legacy System Modernization

Results show that CoSTAR enables small, locally deployable LLMs to achieve performance competitive with substantially larger LLMs for privacy-sensitive COBOL legacy systems.

Hao-Rui Lin, He Jiang, Xiao-Chen Li et al. · 0 citations

Open access Aug 2026

SynaSpace: Behavior-Driven Configuration Optimization of Test Generators for Logic Synthesis Testing

SynaSpace is a behavior-driven configuration optimization framework for fault detection in logic synthesis tools that focuses on synthesis behavior coverage to guide configuration search, by constructing behavioral representations through joint analysis of synthesis logs and gate-level netlists.

Pei-Yu Zou, Xiao-Chen Li, Yijia Meng et al. · ACM Transactions on Design A... · 0 citations