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Author

J. Pandey

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Aug 2026

Design of a Low-Power Self-Biased Continuous-Time Voltage Comparator in 65nm CMOS Technology

The paper presents a self-biased inverter-based continuous-time voltage comparator, implemented in 65 nm CMOS technology using Low Threshold Voltage (LVT) transistors. The proposed design extends a self-biased single-stage reference architecture, and it does this by reusing a centralized bias network across additional...

Akriti Jain, Muskan Mahla, Riyanka Banerjee et al. · 0 citations
Aug 2026

Functional obfuscation of lightweight crypto cores for improved security against IP piracy

Functional obfuscated architectures for the PRESENT, GIFT, and RECTANGLE crypto cores are presented to improve security against IP piracy and demonstrate relative hardware efficiency and integrated IP protection compared with existing designs.

Jugal Gandhi, Diksha Shekhawat, M. Santosh et al. · 0 citations

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