Matej Jurasić

FRISC-V and ApheleiaOS: Running an Operating System on an Extended RISC-V Core Implemented on an FPGA Platform

This paper presents a complete computer system in which both the processor and the operating system were developed by students. The processor, FRISC-V, is a 32-bit RISC-V core that extends an educational RV32I design with the full privileged architecture: machine, supervisor and user modes, Sv32 hardware virtual memory...