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Author

Rajeev Pankaj Nelapati

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Conference Jul 2026

A DMA-Driven Tile-Grid Neural Processing Unit for RISC-V Edge Platforms

Most general purpose processors were never built for the kind of dense arithmetic that neural network inference demands, and running such workloads on a CPU tends to burn power on memory traffic and instruction overhead rather than useful computation. This paper describes a compact neural processing unit (NPU) built to...

Sriskanda Cp, Sucheth N, Rajeev Pankaj Nelapati · 0 citations

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