A DMA-Driven Tile-Grid Neural Processing Unit for RISC-V Edge Platforms

Abstract

Most general purpose processors were never built for the kind of dense arithmetic that neural network inference demands, and running such workloads on a CPU tends to burn power on memory traffic and instruction overhead rather than useful computation. This paper describes a compact neural processing unit (NPU) built to sit alongside a RISC-V core inside a resource-limited SoC. At its core is an 8 × 8 weightstationary systolic array capable of 64 multiply-accumulate (MAC) operations per clock cycle, fed by a four-state DMA controller that moves matrix tiles into two on-chip SRAM buffers without CPU involvement, so the array rarely stalls waiting on data. The RTL was verified in Verilator with cycle-accurate simulation, then carried through Cadence Genus synthesis on a SCL 180 nm standard cell library. The result is a 500 MHz design occupying about $58,236 \mu \mathrm{m}^{2}$ of silicon and reaching a measured peak of $32 \text{GMAC} / \mathrm{s}$ - figures that we believe justify this class of accelerator for tightly area-constrained edge deployments.