Rui-Zhen Pan

R$^{2}$PIAC: A Runtime Reconfigurable Photonic Interconnect Architecture for Chiplet-Based DNN Accelerators

The continued scaling of deep neural networks (DNNs) is driving accelerator architectures toward chiplet-based integration. However, conventional fixed and workload-level optimized topologies do not track fine-grained, time-varying communication during DNN inference, resulting in multi-hop latency and link congestion....