R$^{2}$PIAC: A Runtime Reconfigurable Photonic Interconnect Architecture for Chiplet-Based DNN Accelerators
Abstract
The continued scaling of deep neural networks (DNNs) is driving accelerator architectures toward chiplet-based integration. However, conventional fixed and workload-level optimized topologies do not track fine-grained, time-varying communication during DNN inference, resulting in multi-hop latency and link congestion. To address this challenge, we propose R<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula>PIAC, a runtime-reconfigurable photonic interconnect architecture for chiplet-based DNN accelerators. R<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula>PIAC uses an electro-optic Mach–Zehnder interferometer (EO-MZI) switching fabric to establish high-bandwidth, single-hop lightpaths on demand. To enable runtime reconfiguration, R<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula>PIAC adopts a two-stage heuristic scheduler. The scheduler combines capacity-aware topology matching with utility-driven holding-time selection and uses a cost-aware static fallback to avoid low-benefit reconfigurations for long-tail traffic. We validate R<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula>PIAC through cross-layer hardware–software co-design using a custom <inline-formula><tex-math notation="LaTeX">$8\times 8$</tex-math></inline-formula> EO-MZI switch controlled by a field-programmable gate array (FPGA) and optimized receiver alignment and header qualification. Parallel all-offset alignment and 32-header qualification restore Ethernet packet service within <inline-formula><tex-math notation="LaTeX">$2.0352\;\mu \mathrm{s}$</tex-math></inline-formula> after an optical-circuit reconfiguration. Across five DNN workloads on a four-board, eight-chiplet FPGA prototype, R<inline-formula><tex-math notation="LaTeX">$^{2}$</tex-math></inline-formula>PIAC reduces mean aggregate inter-chiplet service time by 28.22%–63.43% relative to three baselines. The corresponding mean reduction in end-to-end inference latency is 6.14%–18.89%.