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Sponsored AI Networking Cookbook: Practical recipes for AI-assisted network automation and development AI Networking Cookbook: Practical recipes for AI-assisted network automation and development

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S. Aparna

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Open access Jul 2026

Design and Implementation of a High-Speed Three-Operand Binary Adder Using Parallel Prefix Architectures

High-speed and space-efficient arithmetic units are necessary for the hardware implementation of cryptographic algorithms to guarantee security and performance. Efficient multi-operand addition, especially three-operand binary addition, is crucial for modular operations like multiplication and exponentiation. A high-sp...

S. Aparna, C. Padma · 0 citations

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