Design and Implementation of a High-Speed Three-Operand Binary Adder Using Parallel Prefix Architectures

Abstract

High-speed and space-efficient arithmetic units are necessary for the hardware implementation of cryptographic algorithms to guarantee security and performance. Efficient multi-operand addition, especially three-operand binary addition, is crucial for modular operations like multiplication and exponentiation. A high-speed, low-area three-operand binary adder for cryptography and pseudorandom bit generator (PRBG) applications is presented in this study. Kogge-Stone, Han-Carlson, and Ladner-Fischer are examples of parallel prefix adders that are used to increase throughput and decrease propagation latency. For VLSI systems, heterogeneous delay-insensitive coding is used to further optimize power, area, and performance. A Carry Look-Ahead (CLA) adder, which lowers critical route delay through parallel carry generation, is added to the design to improve carry calculation. When compared to traditional designs, the suggested hybrid architecture provides increased speed and efficiency. Its usefulness for high-performance computing and digital signal processing applications is demonstrated via implementation using Xilinx Vivado