Design and Development of a Reliability-Aware Verilog-A LUT Framework for 5 nm Nanosheet SRAM Arrays
This paper presents a TCAD-calibrated, look-uptable-based Verilog-A modeling framework, and uses it to perform a comprehensive reliability analysis of a 4×4 Static Random Access Memory (SRAM) array implemented using Nanosheet Gate-All-Around (GAA) Field-Effect transistor technology, with a focus on device-trap interact...