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S. Pawar

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Aug 2026

Design and Development of a Reliability-Aware Verilog-A LUT Framework for 5 nm Nanosheet SRAM Arrays

This paper presents a TCAD-calibrated, look-uptable-based Verilog-A modeling framework, and uses it to perform a comprehensive reliability analysis of a 4×4 Static Random Access Memory (SRAM) array implemented using Nanosheet Gate-All-Around (GAA) Field-Effect transistor technology, with a focus on device-trap interact...

Charanya Bysani, Parna Lata Chaurasia, S. Yadav et al. · 0 citations

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