Design and Development of a Reliability-Aware Verilog-A LUT Framework for 5 nm Nanosheet SRAM Arrays

Abstract

This paper presents a TCAD-calibrated, look-uptable-based Verilog-A modeling framework, and uses it to perform a comprehensive reliability analysis of a 4×4 Static Random Access Memory (SRAM) array implemented using Nanosheet Gate-All-Around (GAA) Field-Effect transistor technology, with a focus on device-trap interactions and Bias Temperature Instability (BTI) degradation. Trap-induced current degradation is characterized for both band-tail and deep-level interface traps at a concentration of 1 × 1013 cm-2 using Synopsys TCAD device simulations. The degraded drain current characteristics are incorporated into HSPICE circuit simulations via the TCADcalibrated Verilog-A look-up-table model to evaluate SRAM performance metrics such as Write Delay, Hold Noise Margin (HNM), and Read Noise Margin (RNM) under fresh, Positive BTI (PBTI), Negative BTI (NBTI), and combined degradation scenarios. Results show that deep-level traps cause higher current reduction than band-tail traps at the same concentration. Under combined band-tail PBTI and NBTI stress, write delay increases by 16% and HNM decreases by 5.3% relative to the fresh device, while NBTI alone collapses RNM by 48.9% and reduces HNM by 9.3%. Under deep-level trap degradation, write delay increases by up to 47% relative to the fresh device.