This paper describes NexusV, a small, ultra-low-power, 32-bit RV32I+ZiCSR RISC-V softcore microcontroller optimized for resource-constrained embedded systems. The processor employs a deterministic multi-cycle design that timemultiplexes a single Arithmetic Logic Unit (ALU) to minimize datapath logic. Synthesized on the PYNQ-Z2 FPGA board, the core operates at a maximum frequency of 90 MHz, achieving a performance of 0.18 DMIPS/MHz while utilizing only 1,134 LUTs and 406 Flip-Flops. The entire system consumes a highly competitive dynamic power of 18 mW and features a full software ecosystem capable of running C code via the standard RISC-V GCC toolchain. Operational integrity was verified through physical hardware testing and the Dhrystone benchmark alongside integrated AMBA APB3 UART, SPI, and PWM peripherals. These features make NexusV a viable Intellectual Property (IP) core for low-power control units in battery-powered devices.
Prithiviraj Rajalingam, Sudeshna Shettygari, S. S. et al.· 2026 International Conferenc...· 0 citations
SHA-256 is a fundamental hashing algorithm in embedded security, authentication, data integrity verification, and hardware random number generation in resource-constrained systems. This paper presents a quantitative benchmarking study of SHA-256 on the Raspberry Pi RP2350, a microcontroller which has integrated both ARM Cortex-M33 and RISC-V Hazard3 cores on a single die, enabling a direct same-silicon architectural comparison under identical conditions. Throughput, execution time, current draw, and energy per kilobyte were measured across software and hardware-accelerated modes with and without Direct Memory Access on both cores, and against a software baseline on the predecessor RP2040. Hardware acceleration yielded speedups of 14.05\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} and 13.58\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document} over software for the ARM and RISC-V cores respectively, with energy per KB reduced from approximately 25 \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\upmu }$$\end{document}J/KB to under 1.79 \documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$${\upmu }$$\end{document}J/KB in both cases, while current draw remained stable between 17 and 18 mA across all configurations, indicating that efficiency gains are attributable to reduced execution time rather than lower active current. A counter-intuitive observation emerges from the DMA analysis: despite the ARM ecosystem’s significantly greater maturity in embedded bus integration, the ARM Cortex-M33 exhibits a larger DMA-induced throughput penalty (18.1%, factor of 1.221\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}) than the newer RISC-V Hazard3 core (13.6%, factor of 1.157\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times$$\end{document}) when accessing the shared SHA-256 peripheral on identical silicon. To our knowledge, this is the first same-silicon comparison of ARM and RISC-V cryptographic acceleration with direct energy measurements, and the first published per-configuration energy characterization of the RP2350.
Atul Ravi, S. S., B. Kailash et al.· Discover Electronics· 0 citations
