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S. S.

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Conference Jul 2026

Design and Implementation of an Area-Optimized RISC-V Microcontroller with Native APB Interconnect for Low-Power Embedded Applications

This paper describes NexusV, a small, ultra-low-power, 32-bit RV32I+ZiCSR RISC-V softcore microcontroller optimized for resource-constrained embedded systems. The processor employs a deterministic multi-cycle design that timemultiplexes a single Arithmetic Logic Unit (ALU) to minimize datapath logic. Synthesized on the...

Prithiviraj Rajalingam, Sudeshna Shettygari, S. S. et al. · 0 citations
Open access Jul 2026

Comparative energy awareness and performance analysis of ARM and RISC-V SHA-256 hardware acceleration on the RP2350

A quantitative benchmarking study of SHA-256 on the Raspberry Pi RP2350, a microcontroller which has integrated both ARM Cortex-M33 and RISC-V Hazard3 cores on a single die, enabling a direct same-silicon architectural comparison under identical conditions.

Atul Ravi, S. S., B. Kailash et al. · 0 citations

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