Jul 2026· 2026 International Conference on Electronics, Computing, Communication and Control Technology (ICECCC)· pp. 1-7· 0 citations· 19 references
Abstract
This paper describes NexusV, a small, ultra-low-power, 32-bit RV32I+ZiCSR RISC-V softcore microcontroller optimized for resource-constrained embedded systems. The processor employs a deterministic multi-cycle design that timemultiplexes a single Arithmetic Logic Unit (ALU) to minimize datapath logic. Synthesized on the PYNQ-Z2 FPGA board, the core operates at a maximum frequency of 90 MHz, achieving a performance of 0.18 DMIPS/MHz while utilizing only 1,134 LUTs and 406 Flip-Flops. The entire system consumes a highly competitive dynamic power of 18 mW and features a full software ecosystem capable of running C code via the standard RISC-V GCC toolchain. Operational integrity was verified through physical hardware testing and the Dhrystone benchmark alongside integrated AMBA APB3 UART, SPI, and PWM peripherals. These features make NexusV a viable Intellectual Property (IP) core for low-power control units in battery-powered devices.
Puppy, a RISC-V-based System-on-Chip (SoC) targeting energy-efficient edge artificial intelligence (AI) applications, is presented as a validated and accessible solution for intelligent embedded systems.
Gabriela Gouveia, Catherine Pancotto, Ivan Hirata et al.· Journal of Integrated Circui...· 0 citations
The proliferation of Internet of Things (IoT) devices necessitates low-power, on-device processing to overcome the latency, security, and power constraints of cloud-based computation. This paper presents the complete design and physical implementation of a configurable, low-power RISC-V System-on-Chip (SoC) tailored fo...
Luis Eduardo Pereira Mendes, Gabriel Machado Dick, Augusto Kessler Pires et al.· Journal of Integrated Circui...· 0 citations
Embedded processors that can enable sophisticated features like real-time recognition and self-adaptability while adhering to strict power and area limits are necessary due to the Internet of Things (IoT) rapid expansion. The development of adaptable and energy-efficient p rocessing s ystems h as been made possible by...
Chirag M. Rahate, Akanksha Jain, S. Vishvakarma· International Symposium on V...· 0 citations
A low-cost, fully reconfigurable Microcontroller Test Board that provides analytical rigor with accessible hardware to enable measurable experiments in microcontroller labs, and a transparent hands-on laboratory resource for engineering curricula with limited resources.
Omolayo Abegunde, Olúgbénga O. Akinadé, Sunday B. Ogunjide et al.· Applied Sciences· 0 citations
This paper presents a compact FPGA-validated RISC-V SoC for RTOS-oriented embedded prototyping. The fivestage RV32IM_Zicsr base core integrates Gshare prediction, CSR/CLINT interrupts, BRAM memories, MMIO peripherals, and UART. On a Kintex-7 FPGA, the base SoC runs at 250 MHz and uses 3160 LUTs, 2124 FFs, 79 BRAMs, and...
A hierarchical multiplier architecture consisting of partial-product generation, 4–2 compressor-tree reduction, and a look-ahead adder is developed to improve multiplication throughput and reduce latency compared with conventional Wallace-tree implementations.
