Design and Implementation of an Area-Optimized RISC-V Microcontroller with Native APB Interconnect for Low-Power Embedded Applications

Abstract

This paper describes NexusV, a small, ultra-low-power, 32-bit RV32I+ZiCSR RISC-V softcore microcontroller optimized for resource-constrained embedded systems. The processor employs a deterministic multi-cycle design that timemultiplexes a single Arithmetic Logic Unit (ALU) to minimize datapath logic. Synthesized on the PYNQ-Z2 FPGA board, the core operates at a maximum frequency of 90 MHz, achieving a performance of 0.18 DMIPS/MHz while utilizing only 1,134 LUTs and 406 Flip-Flops. The entire system consumes a highly competitive dynamic power of 18 mW and features a full software ecosystem capable of running C code via the standard RISC-V GCC toolchain. Operational integrity was verified through physical hardware testing and the Dhrystone benchmark alongside integrated AMBA APB3 UART, SPI, and PWM peripherals. These features make NexusV a viable Intellectual Property (IP) core for low-power control units in battery-powered devices.