A Compact FPGA-Validated RISC-V SoC with Configurable Z-Extensions for Area-Frequency Balanced RTOS Support

Abstract

This paper presents a compact FPGA-validated RISC-V SoC for RTOS-oriented embedded prototyping. The fivestage RV32IM_Zicsr base core integrates Gshare prediction, CSR/CLINT interrupts, BRAM memories, MMIO peripherals, and UART. On a Kintex-7 FPGA, the base SoC runs at 250 MHz and uses 3160 LUTs, 2124 FFs, 79 BRAMs, and 4 DSPs. It boots RT-Thread Nano and reaches 708.184 Iterations/Sec, or 2.83 CoreMark/MHz, on CoreMark. An optional compile-time Zextension framework covering Zba/Zbb/Zbc/Zbs/Zbkb/Zbkx passed dedicated instruction tests, Spike difftest, and on-board execution. Gshare achieved a 90.37% hit rate and a 4.4% CoreMark/MHz gain over Always Taken.