Yi-Cheng Wu

A Compact FPGA-Validated RISC-V SoC with Configurable Z-Extensions for Area-Frequency Balanced RTOS Support

This paper presents a compact FPGA-validated RISC-V SoC for RTOS-oriented embedded prototyping. The fivestage RV32IM_Zicsr base core integrates Gshare prediction, CSR/CLINT interrupts, BRAM memories, MMIO peripherals, and UART. On a Kintex-7 FPGA, the base SoC runs at 250 MHz and uses 3160 LUTs, 2124 FFs, 79 BRAMs, and...